1. Field of the Invention
The present invention relates to an integrated circuit device such as a logic LSI using a clock signal and, more particularly, to an improvement of an integrated circuit device having a row structure.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional integrated circuit device such as a logic LSI, in which a plurality of rows are arranged parallel to each other, i.e., a so-called row structure logic LSI. More specifically, rows 1 in an LSI 3 respectively include a plurality of logic elements such as flip-flops, registers, and latches, and input/output blocks 5 are arranged at four sides of the LSI 3.
FIG. 2 is a block diagram of a conventional logic LSI employing a macro block structure. In FIG. 2, a plurality of rows are arranged in one block to be parallel to each other, and a plurality of blocks including these rows are arranged in an LSI 3 together with a RAM 31, a ROM 33, and so on. In this LSI, input/output blocks 5 are arranged at four sides.
The internal arrangement and the connection relationship of the plurality of rows are shown in detail in FIG. 3. Referring to FIG. 3, the rows 1 are arranged to be parallel to each other. Each row is connected to a primary power supply wiring 9 and a primary ground wiring 13 through a secondary power supply wiring 15 and a secondary ground wiring 17, respectively. The primary power supply wiring 9 is connected to a power supply through a power supply terminal 7 serving as a part of the input/output block 5. The primary ground wiring 13 is connected or grounded through a ground terminal 11 serving as a part of the input/output block 5 to hold a reference potential. A plurality of logic elements 19 in the plurality of rows 1 are driven by a clock signal. When a hierachical clock driving system is applied, the input terminal of a primary clock driver 23 is connected to a clock signal input terminal 21 serving as a part of the input/output block 5 through a clock signal input wiring 24. The output terminal of the primary clock driver 23 is connected to the input terminals of a plurality of secondary clock drivers 27 through a clock signal input wiring 25. Note that the driving ability of the plurality of secondary clock drivers 27 is generally smaller than that of the primary clock driver 23. The power supply and ground terminals of the primary clock driver 23 are connected to the primary power supply wiring 9 and the primary ground wiring 13 through the secondary power supply wiring 15 and the secondary ground wiring 17, respectively. In addition, the output terminals of the plurality of secondary clock drivers 27 are connected to the plurality of logic elements 19 through clock signal output wirings 29, respectively.
The wiring distances of the clock signal input wiring 25 from the output terminal of the primary clock driver 23 to the input terminals of the plurality of secondary clock drivers 27 are different from each other depending on the position of each secondary clock driver 27. Therefore, a skew of a clock signal may be generated due to the resistance and capacitance of the clock signal input wiring 25. When the skew is generated, the plurality of secondary clock drivers 27 cannot switch synchronously with each other, and hence an operation error may occur.